The overall TPC decoding module design using FPGA, combined with existing AHA4501 chip, and further verify the performance of TPC decoding.

提出FPGA可实现的TPC编译码模块整体设计方案，并结合现有AHA公司的AHA4501芯片，进一步对TPC译码性能进行了验证。

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The main system chips used EP1K100QC208-3, make up of the clock module, control module, time module, data decoding module, display and broadcast module.

系统主芯片采用EP1K100 QC 208 - 3，由时钟模块、控制模块、计时模块、数据译码模块、显示以及报时模块组成。

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Mainly using interpretive mode, it rounded analysis and research majority function which need realized in decoding module, owing to finiteness of hardware resource in embedded system.

由于嵌入式系统硬件资源的有限性，本论文以解释方式为主全面的分析研究了数控系统中译码模块所要实现的绝大部分功能。

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